Hello. I am a researcher at the Strategic CAD Labs at Intel in Hillsboro, Oregon. At Intel I work on high-level modeling and verification of communication protocols and on the synthesis of communication fabrics.
Before joining Intel, I was a
Ph.D. student in
Computer Science at Berkeley
working with Prof. Robert Brayton and
Alan
Mishchenko on logic synthesis and verification. And before Berkeley, I spent a lovely five years
at the Indian Institute of
Technology at Bombay.
| Email: | satrajit.chatterjee [AT] intel.com |
| Office: | RA2-451 2501 NW 229th Ave Hillsboro, OR 97124 |
| Telephone: | +1 971 214-6408 |
The copyright for some of these documents belongs to IEEE, ACM or Springer. They are posted here for your personal use and may not be redistributed.
- A. Gotmanov, S. Chatterjee and M. Kishinevsky. Verifying Deadlock-Freedom of Communication Fabrics. In Proc. VMCAI '11 (to appear).
- S. Chatterjee and M. Kishinevsky. Automatic Generation of Inductive Invariants from High-Level Microarchitectural Models of Communication Fabrics. In Proc. CAV '10, pages 321-338.
- S. Chatterjee, M. Kishinevsky and U.Y. Ogras. Quick Formal Modeling of Communication Fabrics to Enable Verification. In Proc. HLDVT '10, pages 42-49.
- A. Mishchenko, S. Chatterjee, R. Brayton. Boolean factoring and decomposition in logic networks. In Proc. ICCAD '08, pages 38-44.
- A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton. Combinational and sequential mapping with priority cuts. In Proc. ICCAD '07, pages 354-361.
- S. Chatterjee. On Algorithms for Technology Mapping. PhD Thesis, University of California at Berkeley, 2007.
- S. Chatterjee, A. Mishchenko, R. Brayton, and A. Kuehlmann. On resolution proofs for combinational equivalence. In Proc. DAC '07, pages 600-605.
- S. Chatterjee, Z. Wei, A. Mishchenko, and R. Brayton. A linear time algorithm for optimum tree placement. In Proc. IWLS '07, pages 336-342.
- A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to technology mapping for LUT-based FPGAs. In IEEE TCAD, Vol. 26(2), Feb 2007, pages 240-253.
- S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam. Reducing structural bias in technology mapping. In IEEE Trans. CAD, Vol. 25(12), December 2006, pages 2894-2903.
- S. Chatterjee, A. Mishchenko, and R. Brayton. Factor cuts. In Proc. ICCAD '06, pages 143-150.
- A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een. Improvements to combinational equivalence checking. In Proc. ICCAD '06, pages 836-843.
- A. Mishchenko, S. Chatterjee, and R. Brayton. DAG-aware AIG rewriting: A fresh look at combinational logic synthesis. In Proc. DAC '06, pages 532-536.
- A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to technology mapping for LUT-based FPGAs. In Proc. FPGA '06, pages 41-49.
- S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam. Reducing structural bias in technology mapping. In Proc. ICCAD '05, pages 518-525.
- S. Chatterjee and R. Brayton. A new incremental placement algorithm and its application to congestion-aware divisor extraction. In Proc. ICCAD `04, pages 541-548.